It's not just that the 'badlines' steal 40 cycles. They steal a solid block of 40 cycles that cover most of the screen, from end of hblank until just before the right border starts. This blog post [1] has a nice interactive demo showing badline timings.
During a badline it's simply impossible write to the VIC-II's registers during the left border. Though, this seems to indicate it's still possible to open the right border during a bad line, but it's a 1 cycle window (maybe 2).
During a badline it's simply impossible write to the VIC-II's registers during the left border. Though, this seems to indicate it's still possible to open the right border during a bad line, but it's a 1 cycle window (maybe 2).
[1] https://nurpax.github.io/posts/2018-06-19-bintris-on-c64-par...