Intel is not dropping support for it on a lot of CPUs.
The only thing they've done is disable it in the hybrid Alder Lake cores, presumably because the E-cores couldn't support it (while the P-cores could), and they didn't want to deal with the headaches of ISA extensions being supported only on some cores in the system.
> The only thing they've done is disable it in the hybrid Alder Lake cores
That is incorrect. You can buy Alder Lake CPUs that only have one type of core (the i3 series only has P-cores, for example), and those do not support AVX-512 either. They're not "hybrid" in any way.
Some of their motherboard partners initially allowed you to access AVX-512, but Intel has put a stop to this and the feature is disabled on all Alder Lake CPU SKUs, period.
> Intel is not dropping support for it on a lot of CPUs.
That seems like a pretty questionable statement. Intel might keep AVX-512 around for Xeon, but it seems extremely dead on the consumer market. If Intel decides to bring it back for the next generation, that would be strange and very poor planning.
In consumer market, Intel supported AVX-512 only on -X, HEDT processors. There is a rumor that either Adler Lake-X is coming out or it will be folded into Xeon -W workstation line. It will support AVX-512.
It seems likely that the reason is that some intel customers are willing to pai a significant premium for the feature and intel doesn't want it to be available for cheap
If what they’ve done with ECC memory is any indication, this sort of market segmentation would only slow down or even kill adoption of AVX-512 in the consumer sphere. Welp, at least there’s no reliability issue here, so Torvalds is unlikely to get angry anytime soon.
It is disabled in all consumer Alder lake (and I don't remember if there will be Xeon of that gen with P-core only -- IIRC Intel stop the AVX512 validation late on those cores, but it was still before it was formally finished, so probably not). At one point it worked with some Bios on P-core only chips or if you disabled E-core on hybrid ones, but with up-to-date Intel microcode it does not work anymore.
The only thing they've done is disable it in the hybrid Alder Lake cores, presumably because the E-cores couldn't support it (while the P-cores could), and they didn't want to deal with the headaches of ISA extensions being supported only on some cores in the system.