Just wanted to point out that 3nm or 2nm are nothing but the marketing terms. The physical channel length will continue to remain at around 10 nm in this decade, irrespective of the device architecture.
See Fig. 1.2 of my PhD thesis: https://etheses.whiterose.ac.uk/22492/1/Novel%20Approaches%2...
Why is that? What’s the point in calling it “3nm” when it’s not?
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Also, how is that not false advertising then? If I’m told a device is 5nm, and that traditionally meant the gate length, why isn’t it a lie when they’re actually 10nm or whatever? We need to stop calling it “marketing terms” and call it what it is: lies. Just because everyone does it doesn’t make it right.
That is not a great measurement. Transistors can be of different types, each with different value in terms of making products work. Other things matter too: metal, pads, die separation saw cuts, e-fuses, diodes, resistors, and capacitors. Nobody cares about transistors that can't be hooked up to anything.
Well because of tradition. Historically it made sense to define new technology node in terms physical gate length. But now even if that's not viable, they continue to do so for better marketing I guess.
But if we’re not basing it on reality, when does “5nm” become “3nm”? And the fact that it’s just marketing makes comparing across manufacturers (eg. Intel vs. TSMC) impossible.
Short answer is tradition. Historically they were able to stay on Moore's law with each new technology node representing the physical gate length. Currently however, even if they can't continue on that trajectory they still define the next technology node that way.