Besides being able to pack more transistors into a given area, a smaller transistor has less gate capacitance (to first order). This means it can switch faster (smaller RC time constant) and less energy is expended in switching. Thus, going from generation to generation, the overall energy expenditure of a chip can be kept within a reasonable range despite adding many more transistors. You also may have heard of a "die shrink", where an existing design gets shrunk to the next technology node, using less power and clocking faster.
Shrinking isn't always a walk in the park though. Some nodes ago subthreshold leakage became a big problem until they figured out how to solve it.
Smaller distance -> lower resistance -> less heat -> higher clocks/more stuff per clock allowed with same amount of heat produced -> higher performance.
Smaller dimensions means you can set a smaller length for the wire.
As you can see on the diagram on this article, there is a large push into increasing the height of the transistors. That has being going on for more than a decade.
About the width, a finer process means you can keep the width of the most critical transistors the same, but can also trade it off into less width (and performance) where it is less important.
So, overall, smaller dimensions leads to lower resistances. You can trade some of the gain for density, but you'll always get some lower resistance.
None of these reasons are as important as transistor count / mm^2. If you can shrink die size in half, you can effectively reduce its cost by half as well. Processing wafers through 400 steps in the fab and its capacity is limited by how many useful chips you can build on a given 300mm wafer.
Exactly, the smaller your chip is the more you can fit on a silicon wafer.
If your chip is too large it can even make it practically impossible to manufacture at scale due to the increased chance of defects as your chip size increases.
It's crazy to think about if you've never thought about this, but the speed of light is a bottleneck for processors. When we get smaller devices, there's literally less distance that needs to be traversed, so more can be done!
An electrical signal travels close to the speed of light (not the electrons). Even when of course no light travels inside the copper.
If something oscillates at 1 GHz, 15 cm down the wire the phase is opposite. To me it's perfectly correct to say that speed of light affects the design a lot and in many places probably is a bottleneck.
And the "electric signal" is an electromagnetic wave- also known as light. Nowhere did they imply the speed of light in a vacuum, the speed of light in copper is an equally valid interpretation.
More charitably, charge carriers do move much more slowly than the electric field they transmit[0], and while you’re correct that the time-varying electric field in a processor is not light (nor even a radio wave), if the chips were much larger or much higher frequency the chips and buses would risk becoming antennas and having all the problems that would bring — 5 Ghz ~= 6cm wavelength [1] ~= 3cm half-wave dipole.
The numbers roughly correspond to the width of wires in the circuits, but the number of circuits you can fit per unit area depends on the square of that number so going from 7nm to 5nm roughly doubles density. The first microprocessor[1] was around 10,000nm so we're approaching 5,000x thinner wires or almost 25 million times more circuits (the latest Apple M1[2] is at 5nm have about 8,000,000x as many transistors as the 4004).
Smaller distance to travel so signals get from one gate to another quicker which will enable a higher clock speed.
Smaller devices use less power so less heat and longer battery life.
Smaller devices mean a smaller chip which is cheaper (although mask costs will be more expensive) or use the extra area for more features like more cache or another processor core.
With a Fixed Yield, and an exact 100% increase in Transistor Density that translate to 50% smaller Die Size.
On a Wafer, that would equate to Double the amount Die you have. All of a sudden your profits increase dramatically.
5nm also have a better power curve so within the same clock speed you have lower energy usage. Hence you can push for higher performance if needed.
The first point of Uni Economics is important for the industry. If you have high enough volume, say hundreds Million of chips per year then it make sense to move to the next node for cost saving. If you have small volume or low margin chip then the Design Cost, which is the most expensive part of chip making, would not work to your benefits.
And it also depends on Wafer price, If 5nm is Double the Price of 7nm then in the above example your unit cost would be exactly the same.
The second point is important for CPUs, and other things that are increasingly computational expensive like WiFi 6 and 5G Modem. You want your Smartphone to last longer on battery so they work better on an energy efficient node.
So basically it is a Cost / Performance trade offs.
Smaller means closer together. Closer together means less time for a signal to move from one to another. Less time means higher clock speeds.
If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz.
I don't really know enough to refute it, but this seems deeply and bizarrely wrong. It doesn't account for transistor count or density just the size of the entire chip? With pipelining I don't think a signal has to travel across the entire chip every cycle. It also doesn't really address the question above, since single core CPU speeds haven't increased in 15 years even though transistors have kept getting smaller and closer together.
Seems like an intriguing napkin math limit/simplification though, I'd be interested if anyone could elaborate on if there's any substance to it.
The speed of EM signal in copper is roughly 60% of the speed of light. You also have to account for timing jitter and wait until you are sure that everybody has the signal to prevent going out of sync.
This means that reliable distance from a single clock is just a fraction of what the speed of signal theoretically allows.
Clock distribution networks use local clocks to buffer and amplify the global clock but they take a significant amount of chip area and make the chip larger. Clock distribution circuitry draws a significant amount of power. It can be 30-40% of the power usage. You want to use them as little as possible.
It is not wrong, it is rather correct. Speed of propagation in semiconductor materials is at most a third of speed of light in vacuum. So the distance travelled is rather limited for a signal. Also, a signal might have to traverse a few transistors or gates, so frequency in the 3GHz range does really limit processor sizes to the order of millimeters. You already said how to get around it: Pipelines, that limits the area a signal has to propagate. Also, one has to take care to make signals arrive early enough in the longest possible signal path as well as to distribute the clock in a way for it to arrive at aligned times everywhere, so you need a clock distribution net with known delays, etc. Chip timing is black art.
When designing chips or doing layout for FPGA designs, we do something called timing analysis to find out if signals get to where they should do such that the chip is stable ("meets timing").
There is a lot more to it than just distance. The transistors have speeds, to start with.
That and just because this size gives a bound on how quickly you can do things, the transistor count is also increasing, so the actual clock doesn't increase all that much.
> If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz.
100mm across is 10cm, 0.1m, 4 inches. That’s palm-sized CPU - far from any modern silicon.
