ARV32, RISC-V, PowerPC, ARM's Thumb, all variable instruction encoding. The SuperFX came out after the Pentium, the first consumer super-scalar pipelined CISC CPU, and not the first CISC to do it.
None of those are byte opcodes encoding with prefixes.
None of those are variable width depending on what type of argument you have.
Also, PowerPC isn't even variable width at all.
And the Pentium was the first pipelined CISC microprocessor, ie. a single chip. At the time there was a holy war going on with one side being of the opinion that you shouldn't pipeline single chip processors, but instead rely on Moore's law. The thought was that the mainframe style multichip modules needed a pipeline to account for off chip delays, but that all on the same die it was unnecessary and created too unpredictability with pipeline bubbles, etc. Those people were obviously wrong and lost.
Edit: also the Pentium was released a month after StarFox was looking into it. And when you account for the long lead times of hardware, their statements make sense timeline wise. Particularly when you consider that that RISC was a huge buzzword at the time and being misapplied, sort of like how now everybody doing a simple linear regression is talking about all the machine learning they're doing.
Name another RISC with a byte opcode with prefixes and is variable width depending on the arguments. That's about as CISC as you get.
It was pipelined, and at the time people for some reason thought that you couldn't pipeline a CISC and therefore it had to be a RISC.